InPsytech Announces Finalization of Next-Generation UCIe IP Design, Pioneering High-Speed Transmission Technology

Global leader in high-speed interface IP, InPsytech, Inc., has announced significant breakthroughs in performance and efficiency for its Universal Chiplet Interconnect Express (UCIe) product line. The next-generation UCIe physical layer IP, based on TSMC's N4 process, is expected to finalize its design this year. It supports transmission speeds of up to 64 GT/s per lane, demonstrating InPsytech's advanced capabilities in high-bandwidth applications.

Leveraging extensive mass production experience, InPsytech has successfully collaborated with leading AI companies to mass-produce chips using TSMC’s 5nm process, providing robust support for chip design and manufacturing. The new UCIe IP further pushes the boundaries of transmission speed while maintaining exceptional data stability, delivering powerful support for high-bandwidth applications such as artificial intelligence (AI), high-performance computing (HPC), and networking.

InPsytech also announced the successful acquisition of multiple breakthrough patents for UCIe technology. These patents focus on innovative high-speed transmission solutions, including a novel interconnect interface and channel linkage method designed to address reliability challenges in substrate connection channels. Traditional technologies often experience transmission attenuation or interruptions caused by long-term operation or damage. The patented solutions provide a revolutionary approach to these pain points. Another key patent focuses on the automatic detection of output data deviations from safe thresholds, triggering corrective circuits to ensure input data accuracy and stability.

Jason Chen, Senior Vice President of R&D at InPsytech, stated:

“These patents not only highlight InPsytech’s outstanding capabilities in technological innovation but also solidify our leadership in high-speed interface technology. The new UCIe IP, with its groundbreaking transmission speed of 64 GT/s per lane, offers customers reduced design cycles and accelerated time-to-market for their products.”