STM32F103C6T6 Pinout, Architecture, Specifications, & Programming

The STM32F103C6T6 is a low-density STM32F1 microcontroller built around a 72 MHz Arm Cortex-M3 core. Its LQFP-48 configuration provides 32 KB of Flash, 10 KB of SRAM, 37 GPIOs, 10 external channels shared by two 12-bit ADCs, one advanced-control timer, two general-purpose timers, seven DMA channels, and USB, CAN, USART, SPI, and I²C interfaces. It is suitable for compact sensor acquisition, PWM and motor control, and embedded communication systems. ST lists the STM32F103C6 family as active and identifies STM32F103C6T6A and STM32F103C6T6ATR as current LQFP-48 order codes.

Catalog

Figure 1. STM32F103C6T6

STM32F103C6T6 Pinout Functions

The STM32F103C6T6 uses a 48-pin LQFP package and provides 37 GPIO pins. Many GPIO pins support alternate functions, including ADC inputs, PWM outputs, USART, SPI, I²C, CAN, USB, clock signals, and debugging. These functions are selected by configuring the relevant peripheral, the GPIO mode, and the AFIO registers when remapping is required. Functions assigned to the same physical pin cannot be used at the same time.

Figure 2. LQFP48 Pinout for STM32F103x4/x6 Low-Density Devices

Pin	Pin Name	Main and Alternate Functions
1	VBAT	Backup power input for the RTC, 32.768 kHz oscillator, and backup registers when VDD is unavailable.
2	PC13-TAMPER-RTC	GPIO PC13; RTC tamper input or RTC clock output.
3	PC14-OSC32_IN	GPIO PC14; input for the 32.768 kHz LSE crystal or external clock.
4	PC15-OSC32_OUT	GPIO PC15; output for the 32.768 kHz LSE crystal.
5	PD0-OSC_IN	HSE crystal or external high-speed clock input after reset; can be remapped as GPIO PD0.
6	PD1-OSC_OUT	HSE crystal output after reset; can be remapped as GPIO PD1.
7	NRST	Active-low external reset input and reset output.
8	VSSA	Analog ground for the ADC and internal analog circuits.
9	VDDA	Analog supply for the ADC, reset circuits, internal RC oscillators, and PLL.
10	PA0-WKUP	GPIO; standby wake-up input; USART2_CTS; ADC1/ADC2 channel 0; TIM2_CH1 or external trigger.
11	PA1	GPIO; USART2_RTS; ADC1/ADC2 channel 1; TIM2_CH2.
12	PA2	GPIO; USART2_TX; ADC1/ADC2 channel 2; TIM2_CH3.
13	PA3	GPIO; USART2_RX; ADC1/ADC2 channel 3; TIM2_CH4.
14	PA4	GPIO; SPI1_NSS; USART2_CK; ADC1/ADC2 channel 4.
15	PA5	GPIO; SPI1_SCK; ADC1/ADC2 channel 5.
16	PA6	GPIO; SPI1_MISO; ADC1/ADC2 channel 6; TIM3_CH1; remapped TIM1_BKIN.
17	PA7	GPIO; SPI1_MOSI; ADC1/ADC2 channel 7; TIM3_CH2; remapped TIM1_CH1N.
18	PB0	GPIO; ADC1/ADC2 channel 8; TIM3_CH3; remapped TIM1_CH2N.
19	PB1	GPIO; ADC1/ADC2 channel 9; TIM3_CH4; remapped TIM1_CH3N.
20	PB2-BOOT1	GPIO PB2; BOOT1 input used with BOOT0 to select the boot memory.
21	PB10	GPIO; remapped TIM2_CH3.
22	PB11	GPIO; remapped TIM2_CH4.
23	VSS_1	Digital ground.
24	VDD_1	Digital supply for the I/O circuits and internal voltage regulator.
25	PB12	GPIO; TIM1 break input, TIM1_BKIN.
26	PB13	GPIO; TIM1 complementary channel 1 output, TIM1_CH1N.
27	PB14	GPIO; TIM1 complementary channel 2 output, TIM1_CH2N.
28	PB15	GPIO; TIM1 complementary channel 3 output, TIM1_CH3N.
29	PA8	GPIO; USART1_CK; TIM1_CH1; microcontroller clock output, MCO.
30	PA9	GPIO; USART1_TX; TIM1_CH2.
31	PA10	GPIO; USART1_RX; TIM1_CH3.
32	PA11	GPIO; USART1_CTS; CAN_RX; TIM1_CH4; USB_DM.
33	PA12	GPIO; USART1_RTS; CAN_TX; TIM1 external trigger; USB_DP.
34	PA13	JTMS/SWDIO debug signal after reset; usable as GPIO when the debug configuration permits it.
35	VSS_2	Digital ground.
36	VDD_2	Digital supply.
37	PA14	JTCK/SWCLK debug clock after reset; usable as GPIO when the debug configuration permits it.
38	PA15	JTDI after reset; GPIO when JTAG is disabled; remapped TIM2_CH1/ETR or SPI1_NSS.
39	PB3	JTDO/TRACESWO after reset; GPIO; remapped TIM2_CH2 or SPI1_SCK.
40	PB4	NJTRST after reset; GPIO; remapped TIM3_CH1 or SPI1_MISO.
41	PB5	GPIO; I²C1_SMBA; remapped TIM3_CH2 or SPI1_MOSI.
42	PB6	GPIO; I²C1_SCL; remapped USART1_TX.
43	PB7	GPIO; I²C1_SDA; remapped USART1_RX.
44	BOOT0	Boot-mode selection input. Used with PB2/BOOT1 to select User Flash, system memory, or SRAM at startup.
45	PB8	GPIO; remapped I²C1_SCL or CAN_RX.
46	PB9	GPIO; remapped I²C1_SDA or CAN_TX.
47	VSS_3	Digital ground.
48	VDD_3	Digital supply.

Architecture and Working Principles

STM32F103C6T6 Architecture

The STM32F103C6T6 belongs to the STM32F103x4/x6 low-density performance-line family and uses a 32-bit Arm Cortex-M3 core operating at up to 72 MHz. Figure 3 is the official family-level block diagram; therefore, some I/O and ADC counts shown in the diagram represent the maximum available on larger package variants rather than the exact resources of the C6 LQFP48 device.

Figure 3. Official STM32F103x4/x6 Family-Level Block Diagram

The internal bus architecture links the processor, memories, DMA controller, and peripheral buses. The AHB domain connects the Cortex-M3 core, Flash memory, SRAM, and seven-channel DMA controller and can operate at up to 72 MHz. Peripheral functions are divided between the two APB domains. APB1 is limited to 36 MHz, while APB2 can operate at up to 72 MHz. The DMA controller can transfer data between supported peripherals and SRAM without requiring the CPU to move every data item, reducing processor workload during repetitive data transfers.

STM32F103C6T6 Working Principle

Figure 4. Simplified STM32F103C6T6 Working Flow Showing Startup, Data Processing, Interrupts, DMA, Output Control, and Low-Power Modes

The STM32F103C6T6 starts after power-on or reset, selects the boot source, and initially uses the 8 MHz HSI clock. Firmware then configures the system clock, GPIOs, and required peripherals.

During operation, the Cortex-M3 processes input data and controls outputs. DMA can transfer data between supported peripherals and SRAM with less CPU involvement, while the NVIC handles and prioritizes interrupts.

When idle, the device can enter Sleep, Stop, or Standby mode. After Stop-mode wake-up, firmware may need to restore the PLL and selected system clock. Wake-up from Standby causes a reset-style restart.

Technical Specifications

Specification	STM32F103C6T6
Manufacturer	STMicroelectronics
CPU core	32-bit Arm Cortex-M3
Maximum CPU frequency	72 MHz
Flash memory	32 KB
SRAM	10 KB
Main supply voltage	VDD = 2.0–3.6 V
Analog supply with ADC operating	VDDA = 2.4–3.6 V
Backup supply	VBAT = 1.8–3.6 V
GPIO pins	37
ADC	Two 12-bit ADCs sharing 10 external channels; maximum 1 MS/s per ADC with a 14 MHz ADC clock and the minimum 1.5-cycle sampling time
Temperature sensor	Integrated and internally connected to an ADC channel
DMA	Seven-channel DMA controller
Timers	TIM1 advanced-control timer and TIM2/TIM3 general-purpose timers; all are 16-bit
Other timers	24-bit SysTick timer, independent watchdog, and window watchdog
SPI	One SPI interface, up to 18 Mbit/s
I²C	One I²C interface supporting Standard-mode and Fast-mode operation at up to 400 kHz, with SMBus/PMBus support
USART	USART1 up to 4.5 Mbit/s; USART2 up to 2.25 Mbit/s; synchronous mode, LIN, IrDA, and smartcard support
CAN	CAN 2.0B Active controller, up to 1 Mbit/s
USB	USB 2.0 full-speed device at 12 Mbit/s; requires a 48 MHz USB clock. USB-compliant electrical operation requires VDD = 3.0–3.6 V and an external 1.5 kΩ D+ pull-up.
Clock sources	8 MHz HSI, 4–16 MHz HSE crystal, approximately 40 kHz LSI, and 32.768 kHz LSE
RTC	Integrated RTC with backup registers and VBAT operation
Debug interfaces	Serial Wire Debug and JTAG
Low-power modes	Sleep, Stop, and Standby
Additional hardware	CRC calculation unit and 96-bit unique device ID
Package	LQFP-48, 7 × 7 mm body, 0.5 mm pin pitch
Operating temperature	−40 to +85 °C for temperature suffix 6

Note: ST currently lists the STM32F103C6 family as active and identifies STM32F103C6T6A and STM32F103C6T6ATR as current LQFP-48 order codes. For legacy STM32F103C6 devices with a blank internal code after temperature suffix 6 or 7, including STM32F103C6T6, DS5936 Rev. 7, Figure 3, note 1 directs readers to DS5319 for electrical characteristics. Device memory, peripheral counts, and pinout remain defined by DS5936.

Project Setup, Programming, and Debugging

The STM32F103C6T6 is normally programmed and debugged through its Serial Wire Debug (SWD) interface using an ST-LINK probe. Standalone STM32CubeMX is used to configure pins, clocks, and peripherals and generate the project, while STM32CubeIDE provides code editing, building, Flash programming, and debugging.

The menu paths in this section describe the Eclipse/CDT-based STM32CubeIDE 2.2.0, released on June 30, 2026. They do not apply to the separate STM32CubeIDE for VS Code product.

ST-LINK SWD Connections

ST-LINK signal	STM32F103C6T6 connection	LQFP-48 pin
SWDIO	PA13/JTMS/SWDIO	34
SWCLK	PA14/JTCK/SWCLK	37
NRST	NRST — recommended	7
GND	VSS/GND	Any ground
VAPP/VTref	Target 3.3 V rail	Voltage reference

Use a regulated 3.3 V target supply. On a genuine ST-LINK/V2, VAPP/VTref senses the target voltage rather than supplying power to the MCU. Keep BOOT0 low for normal startup from user Flash memory; raising BOOT0 is not required for ST-LINK programming.

Programming Procedure

• Open standalone STM32CubeMX and select the exact STM32F103C6Tx device. Configure the clock, GPIOs, peripherals, and Serial Wire debugging under System Core → SYS.

• Open Project Manager, select STM32CubeIDE under Toolchain/IDE, and generate the code. STM32CubeMX documents the Toolchain/IDE selection as part of the project-generation configuration.

• In Eclipse-based STM32CubeIDE, select File → Import → Import STM32 Project → STM32CubeMX/STM32CubeIDE Project. Select the generated project and complete the import.

• Add the application code inside the designated USER CODE sections, build the project, connect the ST-LINK probe through SWD, and start the debugger. Use breakpoints, stepping, register views, and variable monitoring to verify operation.

For reproducible development and testing, record the STM32CubeIDE version, STM32CubeMX version, STM32CubeF1 firmware package version, compiler and toolchain version, ST-LINK firmware version, and project version used for each build.

STM32F103C6T6 Hardware Design and Validation Checklist

This is a proposed validation procedure, not author-run experimental data. Report the test hardware, operating conditions, raw readings, instruments, and measurement uncertainty.

Minimum Hardware Checklist

• Connect VDD pins 24, 36, and 48 to 3.3 V and VSS pins 23, 35, and 47 to ground. Place one 100 nF capacitor at each VDD/VSS pair and at least 4.7 µF bulk capacitance on the 3.3 V rail.

• Connect VDDA pin 9 to 3.3 V and VSSA pin 8 to ground. Decouple VDDA with 100 nF + 1 µF.

• If VBAT is unused, connect pin 1 to VDD and decouple it with 100 nF.

• Hold BOOT0 pin 44 low with a 10 kΩ pull-down for normal Flash boot.

• Connect NRST pin 7, PA13/SWDIO pin 34, and PA14/SWCLK pin 37 to the SWD interface. Add 100 nF from NRST to ground.

• Use HSI for basic bring-up. Add the appropriate HSE/LSE circuit when required by the final clock configuration.

Minimum-System Schematic

Figure 5. STM32F103C6T6 Minimum-System Schematic

Figure 5 should show all power pins, decoupling capacitors, VDDA/VSSA, VBAT, BOOT0, NRST, and SWD connections.

Test Conditions to Record

Record the board revision, sample count n, repetitions, supply voltage and ripple, ambient temperature, clock configuration, loads, probe setup, instrument accuracy and calibration status, firmware build, STM32Cube versions, compiler version, and ST-LINK firmware version.

Calculation and Validation Checklist

Check	Validation	Report
Power	Measure VDD and VDDA under load and during startup.	Min/max voltage, ripple, uncertainty
Reset/boot	Power-cycle, activate NRST, and verify BOOT0 state.	Reset result and failed starts
SWD	Erase, program, verify, reset, and debug.	Pass/fail and connection failures
ADC	Apply calibrated input voltages and repeat measurements.	Expected code, mean code, spread, error
PWM/timing	Measure frequency and duty cycle.	Calculated value, measured value, error
Communication	Test with a known-good node or loopback.	Bit rate, frame count, errors, duration

For the 12-bit ADC, where VSSA ≈ 0 V:

LSB=V_DDA/4096

N_ideal= min (4095, [ (4096 x V_IN)/V_DDA ] )

where:

• Nideal = ideal ADC code

• VIN = applied ADC input voltage

• VDDA = measured analog supply/reference voltage

The ADC result must remain within 0 to 4095.

Code error = Nmeasured − Nideal

For an edge-aligned, up-counting timer:

fTIM = PCLKx, when the APB prescaler = 1

fTIM = 2 × PCLKx, when the APB prescaler > 1

Then:

fPWM = fTIM/([(PSC + 1) × (ARR + 1)])

For PWM mode 1, active-high operation:

Duty cycle (%) = CCRx/(ARR + 1) x 100

where PSC is the timer prescaler, ARR is the auto-reload value, and CCRx is the capture/compare value.

For measured ADC, PWM, or timing results:

Error (%) = (Measured - Expected)/Expected x 100

Report the signed or absolute error together with the measurement uncertainty and test conditions.

Third-Party Research Case Studies

These case studies summarize third-party research using the STM32F103C6T6. They were not completed or measured by the author of this article.

Magnetic Capsule Control

Wang et al. (2023) used STM32-generated PWM to control three orthogonal Helmholtz-coil pairs through three H-bridge modules rated at 450 W each and supplied at 30 V. The 450 W value was a module rating, not measured power consumption. The system used open-loop control rather than closed-loop current or orientation feedback.

Tests used a Ø25 × 58 mm capsule in a 100 mm water cube. Two cameras recorded motion at 640 × 480 pixels and 60–900 fps. The capsule demonstrated 90° rotations. At 5 mT, the reported maximum soft-magnet torque estimate was 6 × 10⁻⁵ N·m, compared with 5.4 × 10⁻³ N·m for the permanent magnet. Torque was estimated from rotation behavior rather than measured with a torque sensor. Independent specimen count, trial count, uncertainty, and numerical orientation error were not reported.

Source: Wang, Cui, Tian, and Han (2023).

Haptic Touchscreen Control

Kim et al. (2022) used an STM32F103C6T6 to control an electrostatic resonant actuator. One prototype attached to a 125 g block was measured with a 352C66 accelerometer during a 50–200 Hz sweep, reaching 2.5 g at 99 Hz, where g denotes acceleration.

Four actuators were then tested on one 17-inch panel at 25 locations and 90, 117, and 150 Hz, giving 75 location-frequency conditions rather than 75 independent samples. Reported peaks were 1.4 g, 2.6 g, and 1.5 g, respectively. The paper identifies the oscilloscope as DPO2012B in a figure but DPO2021B in the text. Repetitions, uncertainty, human testing, lifetime, and power consumption were not reported.

Source: Kim et al. (2022).

Common Problems and Documented Troubleshooting Steps

Common problem	Likely cause	Documented action
ST-LINK cannot detect the MCU	No target power, incorrect SWD wiring, missing ground, or unsuitable SWD frequency	Confirm target power and SWDIO, SWCLK, GND, NRST, and target-voltage connections. Reduce the debug frequency if necessary.
ST-LINK stopped connecting after programming	Firmware disabled or remapped the debug interface	Use Connect Under Reset with NRST connected to ST-LINK, then erase or replace the faulty firmware. UM2237 specifically identifies this mode as useful when application code disables JTAG/SWD.
Firmware downloads but does not start	BOOT0 is high or an incorrect target configuration is used	Pull BOOT0 low to boot from main Flash, verify the STM32F103C6Tx target, and reset the MCU.
Random resets or unstable operation	Supply dips, inadequate decoupling, electrical noise, or watchdog/reset events	Measure VDD during operation and inspect reset-source flags. Verify the supply, decoupling, grounding, and load-protection requirements described in Section 5 rather than duplicating them here.
MCU fails after clock configuration	Incorrect HSE/PLL configuration, Flash latency, or bus prescalers	For 72 MHz SYSCLK, configure two Flash wait states, keep APB1 at or below 36 MHz, confirm the oscillator and PLLRDY flags before selecting the PLL as SYSCLK, and verify the selected clock source afterward.
UART, PWM, or timer frequency is incorrect	Incorrect clock-tree calculation	Verify the RCC and APB prescalers and calculate the timer clock using the method in Section 5.4.
ADC readings are noisy or inaccurate	Poor VDDA supply, unsuitable sampling time, high source impedance, or missing calibration	Verify VDDA/VSSA integrity, perform ADC calibration, select sufficient sampling time for the source impedance, and keep the input within the permitted ADC range.
PA15, PB3, or PB4 does not work as GPIO	Pins are assigned to JTAG after reset	Configure AFIO to disable JTAG while retaining SWD if debugging is still required.
Program exceeds available memory	Project is configured for a larger STM32F103 variant	Use the STM32F103C6 memory configuration of 32 KB Flash and 10 KB SRAM and review the linker memory report.
I²C device does not acknowledge	Wiring error, wrong address, inadequate pull-ups, incompatible logic voltage, or incorrect timing	Check SDA/SCL wiring, the device address, external pull-ups, logic-voltage levels, and I²C timing with an oscilloscope or logic analyzer.
I²C BUSY flag remains set after power-on or an electrical disturbance	Documented STM32F103x4/x6 I²C analog-filter limitation	Apply the ES0348 §2.8.7 recovery sequence: disable I²C; set SCL/SDA as open-drain GPIO high and verify both high; drive SDA low and verify; drive SCL low and verify; drive SCL high and verify; drive SDA high and verify; restore both pins to alternate-function open-drain; set and then clear SWRST; finally re-enable I²C. Pull-ups alone do not correct this locked-BUSY condition.
A 5 V signal damages or disrupts GPIO	Voltage was applied to a non-FT or analog pin	Only FT-marked digital pins may accept input voltages above VDD within DS5936 limits. For voltages above VDD + 0.3 V, disable the internal pull-up/pull-down resistors. Use level shifting or division for non-FT and analog inputs.
Read protection enabled	Option-byte protection state	Inspect the option bytes using STM32CubeProgrammer. Changing from the protected to the unprotected state by restoring the RDP value causes a mass erase of main Flash. STM32F1 does not use the later irreversible RDP Level 2 scheme.

STM32F103C6T6 vs STM32F103C8T6

The main differences between the STM32F103C6T6 and STM32F103C8T6 are memory capacity and the number of available timers and communication peripherals.

Feature	STM32F103C6T6	STM32F103C8T6
Device density	Low-density	Medium-density
Flash memory	32 KB	64 KB
SRAM	10 KB	20 KB
General-purpose timers	2: TIM2–TIM3	3: TIM2–TIM4
I²C interfaces	1	2
USART interfaces	2	3
SPI interfaces	1	2

The C6T6 and C8T6 share the LQFP48 footprint and STM32F103 architecture, but migration still requires verification of the exact linker script, startup files, alternate functions, peripheral availability, electrical limits, and applicable errata. C8 firmware cannot be moved to C6 unchanged when it exceeds 32 KB of Flash or 10 KB of SRAM, or uses TIM4, I²C2, USART3, or SPI2.

LQFP48 Mechanical Dimensions

Figure 6. LQFP48 7 × 7 mm package outline and mechanical data

The STM32F103C6T6 uses a 48-pin LQFP package with a typical body size of 7 × 7 mm. Its typical overall width, including the leads, is 9 × 9 mm, with a 0.50 mm pin pitch and a maximum package height of 1.60 mm. Each lead is typically 0.60 mm long, with an allowed range of 0.45–0.75 mm.

Note: All dimensions are in millimetres, and the drawing is not to scale. The minimum and maximum values show manufacturing tolerances. Use ST’s recommended PCB footprint instead of calculating the solder pads directly from the package outline. Pin 1 must also match the identification mark on the device.

Technical References

• STMicroelectronics. STM32F103x4, STM32F103x6: Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 com. interfaces. DS5936/DocID15060, Rev. 7, June 2015.

• STMicroelectronics. STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm-based 32-bit MCUs. RM0008, Rev. 21, February 2021.

• STMicroelectronics. STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3 programming manual. PM0056, Rev. 7, December 2024.

• STMicroelectronics. STM32F10xxx Flash memory microcontrollers. PM0075, Rev. 2, August 2012.

• STMicroelectronics. Getting started with STM32F10xxx hardware development. AN2586, Rev. 8, December 2022.

• STMicroelectronics. STM32F103x8, STM32F103xB: Medium-density performance line. DS5319, Rev. 20, July 2025.

Frequently Asked Questions [FAQ]

1. Does STM32F103C6T6 require an external crystal for USB?

A crystal is not a logical requirement, but a standards-compliant USB design needs an accurate 48 MHz PLL clock normally derived from an HSE crystal, resonator, or external clock source. It also requires an external 1.5 kΩ D+ pull-up and the documented USB supply range.

2. Can STM32F103C6T6 be programmed without ST-LINK?

Yes. Set BOOT0 high and BOOT1 low to start the factory system-memory bootloader. It supports programming through USART1 on PA9 and PA10. The factory bootloader does not provide USB DFU for this device, according to AN2606.

3. Can USB and CAN operate simultaneously?

No. USB and CAN share a dedicated 512-byte memory area, so they cannot operate concurrently. They may be included in the same firmware but must be used at different times, as explained in RM0008.

4. Does STM32F103C6T6 include a hardware DAC?

No. Analog-like output can be produced using PWM and a low-pass filter. Use an external DAC when the project requires better accuracy, faster settling, or a stable voltage without PWM ripple.

5. Can STM32F103C6T6 run FreeRTOS?

Yes. FreeRTOS support is supplied through the STM32CubeF1 software package. However, the C6T6 has only 10 KB of SRAM, so task stacks, queues, buffers, and middleware must fit within this limit. Using small task stacks, static allocation, and stack-usage monitoring are engineering recommendations rather than device requirements.